1. Field of the Invention
The present invention relates to a cache memory device, and, more particularly, to a cache memory device which suppresses the occurrence of replacement of data between a cache and a main memory in data processing such as communication control.
2. Description of the Prior Art
A communication control apparatus is provided to mutually connect computer networks constructed by the Ethernet or the like and control mutual communications among the networks. FIG. 6A is a block diagram of a router which is one example of the communication control apparatus and FIG. 6B is a diagram showing the structure of a packet. A header 11 includes information, such as the IP address of a sender and the MAC address of a transmission destination, communication data 12 is a data body to be transmitted, and a trailer 13 includes error check information.
A communication control apparatus 61 receives packet data P1 from a network to which the apparatus 61 is connected, identifies the IP address of a machine/unit which is connected to a network which is where the data is to be sent, selects a route to transfer by referring to a route table, updates the MAC address portion of the header and sends out packet data PO. The following describes an operation that is carried out here. In the communication control apparatus 61, a DMA (Direct Memory Access) 65 transfers a packet 10 received by a network I/O unit 64, connected to a system bus 62, to a main memory 69, constructed by a DRAM, via a memory interface 68 connected to the system bus 62 and writes the packet 10 there, after which a CPU 63 refers to the IP address of the received packet and updates the MAC address. For faster processing of the CPU 63, the communication control apparatus 61 has a cache memory device 67 which constitutes a write-back type secondary cache between the CPU 63 and the main memory 69. Because of the possibility that data in the main memory 69 may be later than data in the secondary cache (cache memory device 67), however, data in the cache memory device 67 is temporarily invalidated by using a cache invalidate command or a coherency protocol command, and then the cache memory device 67 is accessed via a CPU bus 66. As a packet to be accessed is not located in the cache memory device 67 due to the invalidation of the data, the cache memory device 67 reads out data from the main memory 69 via the memory interface 68. Then, the CPU 63 reads out apart of the packet 10 including the header 11 from the cache memory device 67, updates the MAC address portion of the header 11 and writes the resultant data in the cache memory device 67. The packet with the updated header 11 is written back (flushed) into the main memory 69 from the cache memory device 67 in response to a command from the CPU 63, is then transferred via the memory interface 68 and the system bus 62 to the network I/O unit 64 from the main memory 69 by the DMA 65, and is transferred to another network from the network I/O unit 64.
FIG. 7 is an internal block diagram of the conventional cache memory device 67. The cache device 67 has an n-way cache section 72 which includes n (a positive integer equal to or greater than 2) ways from a first way 71-1 to an n-th way 72-n each including m (a positive integer equal to or greater than 2) entries each having a pair of a tag portion for storing a tag address and a data portion for storing data. That is, the cache section 72 includes n ways each capable of storing m tag and data pairs. The cache section 72 may be considered as having m sets that can designate n entries from the first way 71-1 to the n-th way 71-n with the same index address. Although not illustrated, a valid bit which indicates the valid/invalid state of data stored in each entry of the cache section 72 and a dirty bit or the like which indicates a state where data on the cache has been updated but has not been written back into the main memory are provided in association with each entry. The cache memory device 67 further includes n comparison circuits 73-1 to 73-n, an OR circuit 74 and a selection circuit 75. Each of the comparison circuits 73-1 to 73-n detects a match between a tag address stored in a tag portion that is specified by an index address ADI in an address Ad (see FIG. 4B) having a tag field, an index field and a line field and an address ADT of the tag field of the address AD. The OR circuit 74 sets a hit signal HIT active when a match is detected by those comparison circuits and sends the hit signal HIT to a control circuit 77. The selection circuit 75 selects a block of the way (including data of plural lines of line addresses) that corresponds to the comparison circuit which has detected a match when an access made by the CPU 63 is a read access. The cache memory device 67 also includes an LRU (Least Recently Used) memory section 76 that stores a block which belongs to a set comprising blocks of n ways which have the same index address and which has not been used for the longest period of time for each set, as a push-out candidate block LRUB. The control circuit 77 controls writing and reading of a tag address and data to and from the cache section 72, replacement of data and so forth.
In case where the CPU 63 accesses the cache memory device 67 via the CPU bus 66, when none of the tag addresses of n entries in the set that is specified by the index address ADI of the address AD from the CPU 63 coincides with the address ADT of the tag field of the address AD, i.e., when a mishit (or “miss”) has occurred, the push-out candidate block LRUB registered in the LRU memory section 76 is extracted from the set that is indicated by the index address ADI, the tag address and data in the associated entry in the cache section 72 are replaced with the tag field portion and data at the address in the main memory 69 that is indicated by the address AD. Then, data of the block pushed out as the push-out candidate block LRUB from the cache section 72 is sent to the main memory 69 via the system bus 62 and written in the associated area in the main memory 69 where the address ADT of the tag field corresponds to the index address ADI, all under the control of the control circuit 77.
When the CPU 63 makes a write access and detects a hit, dirty information is affixed to write data WD as the associated block in the cache section 72 is rewritten through a switch section 78 controlled by the control circuit 77. The dirty block data is rewritten in the main memory 69 when replacement occurs due to a mishit of an access made by the CPU 63 or the data in the main memory 69 is updated by executing flushing in response to a command from the CPU 63 before being transferred to the network I/O unit 64 from the main memory 69. In case of a mishit, data MD from the main memory 69 is sent to the cache section 72 via the switch section 78 controlled by the control circuit 77 and written there. Then, the CPU 63 performs overwriting of data in the cache section 72 and adds dirty information to the associated entry in the cache section 72.
In the conventional communication control apparatus 61 in FIG. 6A, the CPU 63 can access only the cache memory device 67 via the CPU bus 66 and the network I/O unit 64 can execute DMA with the main memory 69 via the system bus 62. The communication control apparatus 61 therefore requires a process of replacing data of the associated portion into the cache memory device 67 from the main memory 69 for each access made by the CPU 63 or flushing data updated by the CPU 63 into the main memory 69 from the cache memory device 67 prior to transfer to the network I/O unit 64, during a period from the reception of a packet PI from at the network I/O unit 64 to the renewal of its header and transmission of the resultant packet as a packet PO from the network I/O unit 64 by the CPU 63. The communication control apparatus 61 therefore undesirably takes a greater time in data exchange between the cache memory device 67 and the main memory 69 than processing in the CPU 63.
In addition, a portion of communication data 12 which is not used in updating communication control information is stored in the cache section 72 in the conventional cache memory device 67 without being discriminated adequately. This brings about a situation of pushing out data, such as data of a header portion which is likely to be used and data which is to be used when a command code and a command from the CPU are executed from the cache section 72 when communication data which is not used by the CPU is accessed. It is therefore necessary to perform data replacement when the pushed-out header data becomes necessary again. This leads to frequent replacement of data blocks between the cache memory device 67 and the main memory 69, thus lowering the hit ratio of the secondary cache and lowering the performance of the communication control apparatus 61 as a consequence.